Seminar: Networks on Chip Packet-Switching Networks on Systems-on-a-Chip

Nowadays design paradigms of highly complex and integrated Systems-on-a-Chip (SoC) are based on the assembling of predesigned cores and components (Intellectual Property, IP cores). That way, test and development cycles —and finally the time-to-market— can be reduced. To have the manyfold components interoperate with each other in order to get the desired functionality, interconnections between the cores must be established. Thereby several requirements on the communication architecture must be met: Silicon efficiency Short design time Ease of use for the system designer and application developer High performance Low power consumption. Furthermore, even on the same chip we may have different requirements on the communication characteristics from component to component. For audio or video streams for instance, low jitter during communication is necessary. But thinking of a processing unit and a memory module, it is mandatory to have low latency and high bandwidth as well. So, considerations must be taken whether we need best effort or guaranteed throuput, error prone or error free communication on the SoC. The implemented communication architecture shall in any case satisfy all given requirements. Up to now, two approaches mainly addressed the communication architecture on SoCs: Ad hoc wiring of the components and bus based architectures. Whereas bus based wiring may rely on ready-made, standardised buses and interfaces like CoreFrame [11] or AMBA [6], ad hoc wiring requires much more development efforts. A bus is defined as a set of parallel conductors which serves as a common connection for serveral devices. Although buses are suitable for quite a number of applications, they pose a lot of problems when applied to SoCs. As a SoC consists of a variety of different components —each with special requirements to the communication system— it would be necessary to use several parameterized buses on the same chip to fully satisfy all needs. That way, we might have a special high-speed bus for a memory module or a bus with low latency for some sensor data that need to be processed in real time. Indeed, there are solutions like the CoreFRAME or the AMBA bus which base on two different buses, a high-bandwidth bus and a separate bus for slow I/O devices. Thus, bus access of slow devices won't interfere with bus access of high-speed components. But these approaches don't solve the bus inherent problem of long wires: When connecting cores that are far-off from each other, long wires over the whole …